Data transfer between two devices or systems may experience data synchronization problems if the two devices (or systems) do not share a common clock. In order to transfer data between two different clock domains, a strobe may be generated by the sending unit to identify the occurrence (timing) of the data being sent. For example, in source synchronous input/output (I/O) signaling, precisely known data and strobe timing relationship allows the capture of data at the receiver. In one commonly used source synchronous technique, data from the sending unit is coupled to a first-in first-out (FIFO) buffer and strobes from the sending unit trigger the entry points for the FIFO. In this technique, the strobes from the sending unit are coupled to a write state machine, which typically increments the pointer with the receipt of a data strobe. Accordingly, maintaining the integrity of the strobe and the write pointer is of great consequence. Glitches in the strobe, which may be duly recorded by the write pointer, may lead to error in subsequent transfers that may lead to system failure.
Recognizing that errors in data may occur, data may be protected using various known techniques. For example, a parity check procedure may be used to check parity of the received data. However, if the clocking strobes from the sending unit are not similarly protected as the data, then the strobes may compromise the link reliability between the two clock domains. When pointers are used in a write state machine to point to the FIFO entry location for the storage of the incoming data, maintaining the integrity of a strobe and the corresponding write pointer is of significant consequence. As noted above, any glitches in the strobe, absence of a strobe, or other undesirable strobe condition may cause the receiving unit to duly record an unwanted strobe entry or miss a strobe that should have been entered. This improper strobe indication by the write pointer may lead to errors in subsequent data transfers to proper locations in the FIFO unit and may cause severe errors in the core logic.
In order to ensure proper alignment of the FIFO to the incoming data, various strobe protection mechanisms have been devised. For example, in one technique strobe glitch protection and detection circuits are utilized to ensure the proper alignment of the pointer to the incoming data. In one such technique, a counter is used to count the strobe in the core clock domain and this count is checked by insuring that the current count and the previous count is one. In these schemes, an error is flagged and a machine check taken to correct the problem. Other schemes have used a phase lock loop to filter the strobes. However, these various techniques attempt to correct the synchronization timing problem of the pointer by making the adjustment or the correction in the sending clock domain.